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[VHDL-FPGA-Verilog] risc_cpu

Description: 8位risc cpu的编写，使用quartus软件对其进行写入，里面内置乘法器、除法器等模块-8-bit risc cpu the preparation, use the Quartus software to write, which built-in multiplier, divider modules
Platform: | Size: 814080 | Author: 瑞翔 | Hits:

[VHDL-FPGA-Verilog] fadd

Description: 6级流水，verilog实现浮点数的加法，其中浮点数格式符合IEEE754标准-6 water, verilog realize the floating point adder, in which floating-point format in line with the IEEE754 standard
Platform: | Size: 2048 | Author: 兰兰 | Hits:

[VHDL-FPGA-Verilog] c16_multiple

Description: 精通verilog HDL语言编程源码之2--常用乘法器设计-Proficient in verilog HDL source language programming of 2- Common Multiplier
Platform: | Size: 2048 | Author: 李平 | Hits:

[VHDL-FPGA-Verilog] c17_GF_multiple

Description: 精通verilog HDL语言编程源码之3--伽罗华域乘法器设计-Proficient in language programming verilog HDL source of 3- Galois field multiplier design
Platform: | Size: 1024 | Author: 李平 | Hits:

[source in ebook] butfly4

Description: 基4-FFT蝶形单元实现，按照FPGA内部的乘法器功能编写的-4-FFT butterfly-based unit to achieve, in accordance with the internal FPGA multiplier feature prepared
Platform: | Size: 1024 | Author: 苏菲 | Hits:

[VHDL-FPGA-Verilog] fir_parall

Description: 基于verilog的fir滤波器设计，用的并行结构。在前面基础上加入四级流水（加法器，并行乘法器，乘法结果相加两级），通过验证。-Verilog-based design of fir filter using the parallel architecture. In front of the basis of adding four water (adder, parallel multiplier, multiply the result of the sum of two), through the verification.
Platform: | Size: 3072 | Author: 张堃 | Hits:

[VHDL-FPGA-Verilog] Chapter6-9

Description: 第六章到第九章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示。-Chapter VI to Chapter IX of the code in this book through more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of adder/counter, multiplier/divider, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU, etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and results presentation.
Platform: | Size: 6281216 | Author: xiao | Hits:

[VHDL-FPGA-Verilog] Chapter11-13

Description: 第十一章到第十三章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示。-Chapter XI to the 13th chapter of the code in this book through more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of adder/counter, multiplier/divider, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU, etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and results presentation.
Platform: | Size: 5088256 | Author: xiao | Hits:

[VHDL-FPGA-Verilog] 32_bit_complex_multiplier

Description: 一款32位复数乘法器，用verilog写的。-32_bit complex multiplier,written in verilog HDL.
Platform: | Size: 8192 | Author: wilson | Hits:

[VHDL-FPGA-Verilog] booth

Description: booth multiplier in verilog
Platform: | Size: 1024 | Author: s.mohammad jazayeri | Hits:

[VHDL-FPGA-Verilog] multiplier

Description: 8 bits multiplier module in verilog a[7:0]*b[7:0]=c[8:0] // only use one adder
Platform: | Size: 1965056 | Author: ykcir | Hits:

[VHDL-FPGA-Verilog] complex-mul

Description: complex multiplier in verilog code is uploaded
Platform: | Size: 1024 | Author: rashmi | Hits:

[VHDL-FPGA-Verilog] Chapter16-Multiplier

Description: 书籍《精通Verilog HDL语言编程》中第16章的程序实例代码，是关于常用乘法器的设计的，对于初学者有一定的帮助-Book "Proficient in Verilog HDL language programming" in Chapter 16 of the procedure code, the common multiplier designed for beginners will certainly help
Platform: | Size: 3072 | Author: vb | Hits:

[VHDL-FPGA-Verilog] serial_multiplier

Description: Module for Sequential multiplier in verilog
Platform: | Size: 3072 | Author: uma | Hits:

[VHDL-FPGA-Verilog] wallace_tree_multiplier

Description: this implements wallace tree multiplier in verilog
Platform: | Size: 3072 | Author: ashwanth | Hits:

[VHDL-FPGA-Verilog] multiplier

Description: 4x4 multiplxer in verilog
Platform: | Size: 428032 | Author: KinKer | Hits:

[Other] SEQ_MULT

Description: SEQUENTIAL MULTIPLIER IN VERILOG USING BOOTH S ALGORITHM
Platform: | Size: 1024 | Author: Nik | Hits:

[Other] mux16

Description: 用verilog写的乘法器，在quartus里可以直接运行，有详细注释(Multiplier written in Verilog, in quartus can run directly, with detailed notes)
Platform: | Size: 119808 | Author: 万寿吾江1 | Hits:

[VHDL-FPGA-Verilog] float_mult32x32.v

Description: verilog 语言写的FPGA内部实现硬件浮点乘法器的源码，两个时钟周期完成一次浮点乘法运算(The FPGA language written in Verilog implements the source of the hardware floating point multiplier, and completes the floating point multiplication operation in two clock cycles.)
Platform: | Size: 1024 | Author: orangell | Hits:

[VHDL-FPGA-Verilog] multiplier

Description: Booth乘法器是属于位操作乘法器，采用流水线结构实现(The Booth multiplier is a bit-operated multiplier that is implemented in a pipeline structure.)
Platform: | Size: 2138112 | Author: wlkid1412 | Hits:
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